After 5 long years we finally made it back to Nippon 🌸
To continue my tradition of odd travel photo themes (see above link), below are some interstitial spaces between buildings. I always found these to be quite interesting, as seeing something like this is rare in spacious Melbourne.
Feels odd to realize that it's been 9 months since the last update, and oh boy what an interesting 9 months it's been... But through all this chaos we have managed to make some fun memories with the little one, memories that somehow feel that bit more special then before 🥲
One thing we quickly realised is that we have way less time on our hands (surprise surprise), as our "free" time is now either catching up on chores/admin or trying to recharge our mental batteries. But as always we have found ways to adapt to the new situation (or so we claim), whether it be by improving project workflow/tracking or outsourcing tasks where/when possible.
So in this update I want to first talk about the former, improving project workflow, specifically how I now plan to use Altium Designer when working on PCBAs. Then to finish things off, I will show some snapshots of projects I have miraculously found the time to work on :O
Looking back, my PCBA design workflow was not that efficient, which I guess was not a huge deal at the time... But now that free time is that bit harder to come by, I have tried to optimize a number of aspects. For example:
|
Old
workflow |
Revised
workflow |
|
|
Altium
component creation & management |
A
SCH symbol & PCB footprint would be linked up in a relevant schematic
library (SchLib), of which there were 12 (res, cap, IC…). SCH
symbols would typically be reused, but would be copied from one component to
another. So updating a SCH symbol used by many components was very tedious
as I had to update each one manually. PCB
footprints would always be created from scratch, as I could not easily check if a
footprint already existed until I generated it (usually via IPC Compliant
Footprint Wizard). |
All
components are now managed by a single database library (DbLib), which I edit
via Microsoft Access. This makes it very easy to link up a single SCH symbol
and/or PCB footprint to many components, so creating a new component is now
much quicker. Since everything is linked up by a database, if I want to update a SCH symbol or a PCB footprint that's used by many parts all I have to do is make a single edit. Lastly, PCB footprints (and their name) are created based on manufacturers recommendation (vs going direct to IPC Compliant Footprint Wizard). Making it easier to see if an existing footprint is present in the database. |
|
Altium
project creation |
When
creating a new Altium PRJ, I would first try to find a previous project that
somewhat resembled what I was hoping to achieve. Then I would manually copy
and modify all the project files (SCH, PCB, BOM…) & individual
parameters… Inevitably missing something crucial along the way. |
I
now have an Altium PRJ template which automatically adds all relevant files
(SCH, PCB, BOM…) when a project is created. Plus, all linked files now
reference the project parameters, making it very easy to update project
revisions & release datapacks. |
|
Altium
project release (datapack generation) |
Once
a project was finalised, I would manually go over all line items in the
ActiveBOM and allocate a manufacturing part number to those that did not have
one (like jelly bean resistors & capacitors that used a generic
component). With
the ActiveBOM configured I would then create the project datapack (PCB FAB
& ASSY files) by manually generating each output container in the OutJob.
With 7 containers this meant 7 individual clicks, not including
setting up the container names. |
Now that all components are managed by a database library (DbLib), it's much easier to lock in the key details (MPN plus two alternative) during component creation. So, no more fiddling with ActiveBOM where MPN info would be lost between projects. Lastly,
datapack generation is now handled by the Project Releaser, which configures the output containers (PCB FAB, PCB ASSY, PRJ validation &
snapshot…) based on project parameters. Letting me generate a datapack with
the click of a single button :D |
With all that said, the next step is to use the revised workflow & templates for my Prusa XL side filament sensor mod. But since Prusa have not yet shared the design files (like with the MK3S), I will have to get the printer first before I can make any major progress.
As promised, here are some snapshots of projects I have found the time to work on:
1. AR2 Barrel is nearly complete, just putting on the finishing touches (LED diffusers, shell fingers, spring holder...)
2. Waifu decided to hold her first DnD campaign and asked me to design and 3D print some props
3. Fortifying the work area because someone has learned how to crawl ; - ;
Feels like this year is going to be a bit of a slow one in terms of blog updates, see if you can figure out why below 🙃
Last year we got the Minbie Steriliser & Dryer v1, a compact baby bottle steriliser. And this year we found just how loud the piezo buzzer is... which is a bit odd considering some parents/bubs are easily woken up D:
Luckily this one was an easily fix, just add an in-line potentiometer to adjust the volume:
Last year my work held the annual birthday party at the Melbourne Museum Science and Life Gallery, with the theme being "Night at the Museum, Moments, Figures and Natural History". For my costume I decided to go as an "alien disguised as a museum cleaner", which I showed with a rather nifty headpiece (see video below)
The costume managed to win the "Most Innovative Costume" award, which was a pleasant surprise :D
After many late nights and long train rides the AR2 Barrel electronics are complete! For those curious the electronics assembly consists of 4 PCBAs:
BARREL_MAIN-BOARD
BARREL_LED-CARRIER-CENTRE
BARREL_LED-CARRIER-FRONT
BARREL_LED-CARRIER-REAR
And here's how the AR2 Barrel MECH & ELEC assembly looks like:
Just like with the RECEIVER_MAIN-BOARD I want to give a quick rundown of what I am happy with and what I know could be better (you know... have I had more time). But before getting into the nitty gritty here is a cool timelapse of the board being laid out in Altium:
All of my switching regulators and complementary EMI filters are located on the bottom side, away from the "sensitive" digital zones on top layer. ~0.2mm below the bottom layer I have a solid 0V reference plane, ensuring that the high energy current traces have a closely coupled return path (think small current loop area, translating to lower emissions)
And for those tracks that change their reference plane (as in jump from bottom to top layer), I make sure to use a 1N stitching capacitor to assist with the return path. More on this in the BAD section
Previously I was using 0603 sized ceramic capacitors for decoupling, filtering, & general bulk storage. A downside of such a "small" package (depending who you ask) is that with a typical X5R/X7R dielectric the capacitance will be dependant on bias voltage (and temperature), something most manufacturers don't show in their datasheet:
NOTE: Electrolytic & tantalum capacitors also have this behaviour, and from memory polymer versions of the two are not as impacted. But as always you need to check the datasheet to know what to expect... as you can get drastically different performance with same dielectric material
Is this a problem? As always, it depends on the application. But here are a couple of solutions/scenarios if I wanted to stick with using a ceramic capacitors:
An improvement to my previous design the EMI filter topology has been changed from pi to T. Which is more appropriate when source & load impedances are LOW (like they are here)
I am very happy with my 0V reference plane (bottom side tracks), but I don't have the same enthusiasm for the reference plane used by the top side tracks... as the thing is incredibly choppy:
What does this mean? Well I can expect to see increased emissions, as the return current for each trace can no longer run directly underneath. James Pawson of Unit 3 Compliance has a really good video on this, but below are some key slides to explain the issue:
To help this discontinuity in return path I have sprinkled as many reference plane stitching capacitors as I can across the board. But now that I think of it I should have just poured 0V on the top side and stitched it to the internal 0V reference plane with a matrix of vias, spaced to reflect the highest frequency of concern
Though I am quite happy with the tight layout on the bottom side, once the LED related nets make their way to the top side the trace lengths become unpleasantly long due to the connector positions. Again I can expect increased emissions due to the larger loop area D:
An easy solution would be to move the connectors (not possible), or throw more layers at the board
J101 could easily have a common mode choke on all 3 data lines, as each pin has a 0V conductor next to them...
J102, P100, & P101 do not have a filter at all... So expect worse emissions (EM noise getting out) & susceptibility (EM noise getting in) performance here
And to close it all off, here are the BARREL_MAIN-BOARD schematics:
And the PCBAs
