Having completed a good portion of the AR2 receiver model I decided to put on my Altium hat and work on the PCBA's. The first board I designed was the RECEIVER_SENSOR-LEFT, which houses the:
- IR LED emitter pair (used for sensing the solenoid plunger position, see here for explanation)
- Trigger debouncing circuit (I am using a snap action switch which is notorious for being "bouncy" when changing states)
You can see the location of this board below:
As I was designing the first board I realised that I did not have a solid overview of what other PCBA's will be inside the AR2. Looking back this is something I should have figured out earlier on, especially with a multi-board design like this. And though I had a simple overview posted here, I figured this was not detailed enough...
With all that said here is how each PCBA will be connected, as well as where it will be located:
Power Filter
From the block diagram above you can see that the reciever will house 3 boards:
- RECEIVER_MAIN-BOARD (primary/mother board)
- RECEIVER_SENSOR-LEFT (secondary/daughter board shown in video)
- RECEIVER_SENSOR-RIGHT (secondary/daughter board)
The plan is to generate the power rail (3.3V) on the primary board and then feed it into the secondary board via a ribbon cable, the length of which would be ~30mm. Now, under normal circumstances (as in with a simple project) I would feed in the rail directly as the ribbon cable is relatively "short", but this time I wanted to have a bit of fun and play around with some pi-filter combinations in LTspice. To make the simulation more "realistic" I also accounted for cable, capacitor, & ferrite bead parasitics (resistance, inductance, & capacitance), as these would have an impact on ripple/noise attenuation. For example here is how it looks without any filter present:
NOTE: Below simulations are not ideal for a power filter (should be using step response), see next blog post for new simulations
I should note that with my simulations I am assuming that most of the parasitic elements come from the cable (as in parasitic elements from connector interface and PCB traces/planes are "negligible"). Anyway, after doing a fair bit of research and running many simulations this is the pi-filter combination I narrowed in on:
Here I form a pi-filter with a 10μF electrolytic capacitor, a 33Ω (@100MHz) ferrite bead, and a 10μF ceramic capacitor. The "high ESR" electrolytic capacitor helps to dampen/attenuate any ripple on the power rail; you can achieve similar attenuation by adding an inline resistor but as you would imagine this adds voltage drop to the rail. Also, I went with this configuration as it has a fairly steady phase shift across all frequencies, as in there is no sudden 180° phase shift which would introduce sharp peaks (see below)
Finally, here are some extra combinations that did not make the cut (kinda interesting to see what happens if you only use ceramic or electrolytic capacitors):
And for those still curious, here is what happens when you add a 100nF ceramic capacitor at the output:
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